JP-A-2011-171753 (PTL 1), U.S. Pat. No. 6,535,453 (PTL 2) corresponding thereto, JP-A-2003-297953 (PTL 3), U.S. Pat. No. 8,238,142 (PTL 4) corresponding thereto, or JP-A-2002-43441 (PTL 5) relates to a multi-port SRAM. The above documents disclose an SRAM circuit having a differential dual port or a triple port having two isolated single ended read ports, an SRAM layout in which the central portion of a cell is formed as an N-type well region and a P-type well region is arranged on both sides thereof, and the like.
Similarly, JP-A-2008-211077 (PTL 6) relates to a multi-port SRAM. The above document discloses an SRAM circuit of various types of triple port, and a cell layout corresponding thereto.
Similarly, JP-A-2011-35398 (PTL 7) or U.S. Pat. No. 8,009,463 (PTL 8) corresponding thereto relates to a multi-port SRAM. As an example of the cell layout of a dual-port SRAM, the above documents disclose an example in which a grounding line is arranged between bit lines in parallel thereto.